1. Field of the Invention
The present invention relates to dynamic logic circuits, and in particular, to dynamic logic circuits operating with low power supply voltages.
2. Description of the Related Art
Dynamic logic circuitry using complementary metal oxide semiconductor field effect transistors (C-MOSFETs) has seen ever increasing use in recent years because of its advantages of low power consumption, high speed capabilities and small layout area requirements. One common logic cell in such circuits consists of a single P-type MOSFET (P-MOSFET) with a clock input, an N-type MOSFET (N-MOSFET) logic circuit with one or more N-MOSFETs with one or more logic inputs, and a single N-MOSFET with a clock input. The output node is precharged to approximately the power supply voltage VDD by the P-MOSFET and is conditionally discharged to the circuit reference VSS by the logic circuit in cooperation with the single N-MOSFET in accordance with a single-phase clock. The precharge phase occurs when the clock is low (logic 0), thereby turning on the P-MOSFET "precharge" transistor, and the "evaluate" phase occurs when the clock is high (logic 1), thereby turning on the single N-MOSFET "discharge" transistor, or "ground switch." Frequently, a static C-MOSFET inverter cell follows this logic cell so as to allow a single clock signal to precharge and evaluate a cascaded set of such dynamic logic blocks. This type of dynamic logic is often referred to as "domino" logic, further discussion of which can be found in N. H. E. Weste and K. Eshraghian, "Principles of CMOS VLSI Design, A Systems Perspective (Second Edition)," Addison-Wesley Publishing Company, 1993, pp. 301-11 (incorporated herein by reference).
As MOSFET technology has evolved, individual MOSFETs have become steadily smaller, e.g. with smaller feature sizes, particularly shorter channel lengths. This has allowed more and more MOSFETs to be integrated together in one integrated circuit (IC), as well as allow the requisite power supply voltage (VDD) to become smaller as well. Benefits of the former include reduced size and increased operating frequencies, while benefits of the latter include reduced power consumption. However, operating MOSFETs at today's lower power supply voltages has the undesirable effect of lowering MOSFET current which reduces the maximum operating frequency. Hence, in order to minimize reductions in circuit performance, the MOSFET threshold voltages (V.sub.TH) are reduced so as to minimize reductions in the MOSFET current. (Further discussion of the relationship(s) between power supply voltage, threshold voltage and operating performance for MOSFETs can be found in commonly assigned, copending U.S. patent application Ser. No. 08/292,513, filed Aug. 18, 1994, and entitled "Low Power, High Performance Junction Transistor", the disclosure of which is hereby incorporated herein by reference.) However, this in turn has the undesired effect of increasing MOSFET leakage current, i.e. MOSFET current flowing when the device is turned off. This results in charges leaking to and from the output node of each logic cell which prevents output signal levels from achieving and maintaining full VDD and VSS values, thereby decreasing noise immunity and increasing chances of failure due to data losses caused by charges leaking to or from the output nodes.
Accordingly, it would be desirable to have a dynamic logic circuit having transistors with reduced threshold voltages so as to take maximum advantage of the benefits available from the use of lower power supply voltages while simultaneously minimizing chances of failure due to data losses caused by charge leakage to or from data storage nodes, minimizing reductions in maximum operating frequency and providing improved output signal levels for improved noise immunity.